This invention relates to a semiconductor memory device comprising a redundant or spare array of redundant memory cells arranged in a rectangular matrix for use in substitution for a faulty element of an ordinary or normally used array of ordinary memory cells placed in a square matrix.
A conventional semiconductor memory device of this type is disclosed in Japanese Patent Prepublication (A) No. 273,298 of 1989. In the manner which will later be described in greater detail, this semiconductor memory device comprises an ordinary array comprising ordinary memory cells in M ordinary columns and E ordinary rows, where M represents a first predetermined integer and will later be represented alternatively by N. A redundant array comprises redundant memory cells in P redundant columns and Q redundant rows, where P and Q represent second and third predetermined integers. Either of the second and the third predetermined integers is usually equal to the first predetermined integer. Throughout the following, either of the columns and the rows will be called links. At least one of the ordinary and the redundant links may or may not include a faulty link which includes, for example, a faulty memory cell. The first predetermined integer is alternatively called a first plurality. A second plurality refers to P or Q used for the redundant links, from which a faulty redundant link may be excluded.
A faulty address indicating circuit is referred to in the Japanese Patent Prepublication as a fuse and indicates an address of the faulty ordinary or redundant link. The fuse may comprise a certain number of fuse elements, each of which breaks when an excessive electric current flows typically through in ordinary link. In this event, the link in question is deemed as the faulty link.
Connected to the ordinary array, in ordinary link selecting circuit or decoder is supplied with an ordinary link address signal indicative of a selected link among the ordinary links and selects the selected link from the ordinary links at a time unless this operation is inhibited in the manner which will presently be described. Connected to the redundant array, a redundant link selecting circuit includes the faulty indicating circuit to activate a redundant circuitry activating signal by using a skillful circuit which will later become clear. Redundant circuitry refers primarily to the redundant array. Supplied with the ordinary link address signal, the redundant link selecting circuit selects a substitution link among the redundant links for use in substitution for one of the ordinary links that is indicated as the faulty link by the faulty address indicating circuit. The redundant circuitry activating signal Is delivered to the ordinary link selecting circuit. When the redundant circuitry activating signal is activated, the ordinary link selecting circuit selects none Of the ordinary links. Otherwise, the ordinary link selecting circuit is operable in the manner described before.
Although not described in the Japanese Patent Prepublication, the semiconductor memory device may comprise first and second memory blocks, each comprising the ordinary and the redundant arrays of the type described. This is the case when the semiconductor memory device has a large memory capacity to be, for example, a dynamic random access memory (DRAM) of four megabits or more. In this event, the faulty address indicating circuit and the ordinary and the redundant link selecting circuits may be used in common to the first and the second memory blocks. In order to put the semiconductor memory device in normal operation of an address structure among different bit structures, an address format switch signal is used as a block switch signal to make an address format switching circuit selectively put either both of or a selected block of the memory blocks.
Alternatively, the semiconductor memory device of the large memory capacity is used in a word structure, such as N bits by 2N words and (N+1) bits by N words with a word format switch signal used as the block switch signal. In this event, an R/W (read/write) control circuit Is used in each of the memory blocks to R/W access the ordinary and the redundant arrays in compliance with a control signal produced in response to the word format switch signal and to an additional row address signal indicative of an (N+1)-th ordinary row. In common to the first and the second memory blocks, a word format switching circuit is used to produce the control signal as a first and a second control signal which are not and are accompanied by the additional row address signal. Accessed by the R/W control circuits supplied with the first control signal, the ordinary arrays of the first and the second memory blocks are collectively used as an N-bit by 2N-word structure. Controlled by the second control signal, these ordinary arrays are individually accessed substantially as an (N+1)-bit by N-word structure.
Use of the redundant array or arrays is desirable in order to raise a yield of manufacture. In practice, the semiconductor memory device is tested before completely manufactured. In order to carry out the test, the semiconductor device is put in a test mode of operation by a test mode signal. Before put in the test mode, the ordinary links are successively tested by using the ordinary link address signal. If a faulty link is found during the test, the faulty address indicating circuit is made to indicate the address of the faulty link. Put in the test mode, the redundant links are successively tested by again using the ordinary link address signal. After the test for the redundant array, it is possible to use the semiconductor memory device as one including no fault or defect.
In the conventional semiconductor memory device disclosed in the Japanese Patent Prepublication, the skillful circuit is used in consideration of the test mode signal for the redundant array. Test of the ordinary array is, however, impossible in the meanwhile and must be carried out in a different mode of operation. It therefore takes a long test time. On putting the conventional semiconductor memory device into this different mode of operation, a complicated circuit and pads for additional test signals must be manufactured on a semiconductor chip. This necessitates a wide chip area. In addition, the test mode signal and the additional test signals must have specific patterns. Such disadvantages are experienced also in the semiconductor memory device comprising a plurality of memory blocks.